The LCD is a commonly-used panel display, wherein the Thin Film Transistor Liquid Crystal Display (TFT-LCD) is the mainstream product in the current liquid crystal displays. With the increasingly fierce competition in the TFT-LCD products, the manufacturers have to reduce the cost of their products by using new techniques, so as to enhance the market competitiveness of the products. Wherein, GOA (Gate on Array) technique refers to integrating a gate driver of TFT-LCD on an array substrate, thereby forming a scan driving of the panel. Compared with the traditional COF (Chip On Flex/Film) process and the COG (Chip On Glass) process, it not only can save cost, but also can achieve a beautiful design of symmetry of both sides, leaving out binding region and fan-out wiring space of a gate integrated circuit (Gate IC), thereby achieving a narrow border design. At the same time, a Gate direction binding process can be saved, which is more favorable for enhancing the productivity and yield.
However, compared to the COF and COG techniques, GOA technique also has some problems. An existing gate driving circuit includes shift registers at a plurality of stages, and FIG. 1 is a structure diagram of the shift register at each stage in the existing gate driving circuit. As shown in FIG. 1, said shift register at each stage comprises a first TFT switching device M1, a second TFT switching device M2, a third TFT switching device M3, a fourth TFT switching device M4, a pull-down unit PD and a boost device C1; wherein a drain and a gate of M1 is connected to an input terminal (INPUT), and receives an output signal of the shift register at a previous stage; a drain of M2 is connected to a source of M1, a gate of M2 is connected to a reset terminal (RESET) and receives an output signal of the shift register at a next stage, and a source of M2 is connected to a low-voltage signal terminal (VSS) and receives a low-voltage signal; a drain of M3 is connected to a clock signal terminal, a gate of M3 is connected to the source of M1, and a source of M3 serves as a signal output terminal (OUTPUT) of the shift register at the present stage; a drain of M4 is connected to the source of M3, a gate of M4 is connected to the reset terminal (RESET), and a drain of M4 is connected to the low-voltage signal terminal (VSS); one terminal of C1 is connected respectively to the source of M1 and the gate of M3, and the other terminal of C1 is connected to the source of M3; the pull-down unit PD is not only in parallel with C1, but also one terminal thereof is connected to the low-voltage signal terminal (VSS), and another terminal is connected to the drain of M3.
The operational principle of the aforementioned gate driving circuit is: when an input signal at INPUT is at a high level, M1 is turned on, and a node PU is charged; when a clock signal at the clock signal terminal is at the high level, M3 is turned on, the pulse of the clock signal is outputted at OUTPUT, and at the same time the node PU is further pulled up due to bootstrapping of C1; thereafter M2 and M4 are turned on by a reset signal at RESET, so as to discharge the node PU and OUTPUT. Next, the circuit devices of the pull-down unit PD are controlled by the clock signal to discharge the node PU and OUTPUT, ensuring that there will be no noise occurring in the line corresponding to the shift register at the present stage during the non-operating time, the specific timing sequence of respective signals being as shown in FIG. 2. In normal circumstances, when the shift register shown in FIG. 1 is applied, at the instant of TFT being turned off, the signal at OUTPUT jumps from the high level to a low level, and the voltage jump of the pixel is large, thus affecting the picture quality of LCD.
In normal circumstances, it may be considered to add the function of a multi-level gate (MLG) to the gate driving circuit, so as to reduce the voltage jump and improve the picture quality. The generation principle of MLG is to draw a feedback signal from the output terminal to DC/DC IC and subsequently to generate a voltage and output it.
However, α-Si process is typically adopted in the existing gate driving circuit. Considering the mobility of TFT in the α-Si process under a low-temperature condition will drop by about half compared to that under a high-temperature condition, therefore, in order to avoid the situation of failure occurring when the gate driving circuit is in the low-temperature condition, a solution of adding a temperature compensation circuit outside of the gate driving circuit is usually adopted, and particularly a thermo-sensitive device can be connected in parallel with the feedback circuit generating the gate high level Vgh to cause Vgh to rise with the temperature falling down.
However, once the effectiveness of the gate driving circuit is guaranteed by way of using temperature compensation, the voltage of Vgh may rise to more than 30V, while DC/DC IC cannot withstand such a high voltage, and in this case the function of MLG will be deactivated. Once the function of MLG is deactivated, there will be a large voltage jump at the instant of TFT being turned off, thus affecting the picture quality of TFT panel.